TESTBENCH 语法参考

always
module clock_gen;

reg clock;

//Initialize clock at time zero
initial
clock = 1'b0;

//Toggle clock every half cycle (time period = 20)
always
#10 clock = ~clock;

initial
#1000 $finish;

endmodule


forever
module synchronize;
//Example 2: Synchronize two register values at every positive edge of
//clock
reg clock;
reg x, y;

initial
begin
clock = 1'b0;
x = 1'b0;
y = 1'b0;
#100000 $finish;
end

always #5 clock = ~clock;
always #11 y = ~y;

initial
forever @(posedge clock) x = y;

endmodule

initial
module stimulus;
reg x,y, a,b, m;

initial
m = 1'b0; //single statement; does not need to be grouped

initial
begin
#5 a = 1'b1; //multiple statements; need to be grouped
#25 b = 1'b0;
end

initial
begin
#10 x = 1'b0;
#25 y = 1'b1;
end

initial
#50 $finish;

endmodule
 

repeat
//Illustration 2 : Data buffer module example
//After it receives a data_start signal.
//Reads data for next 8 cycles.

module data_buffer(data_start, data, clock);

parameter cycles = 8;
input data_start;
input [15:0] data;
input clock;

reg [15:0] buffer [0:7];
integer i;

always @(posedge clock)
begin
if(data_start) //data start signal is true
begin
i = 0;
repeat(cycles) //Store data at the posedge of next 8 clock
//cycles
begin
@(posedge clock) buffer[i] = data; //waits till next
// posedge to latch data
i = i + 1;
end
end
end

endmodule