用EPM7128可是实现对光电编码器的4倍频，实现的原理是利用状态机实现的，判断A B的电平的变化。
与单片即的接口很简单，利用8位地址总线，+2个地址线 A0 A1.

用51做的采集模块，通过串口发数据给上位机。

参考文献《光电编码器在电机检测中的应用》
刘阳  吴敏  曹卫华
（中南大学信息科学与工程学院   长沙   410083）
摘要：本文介绍了电机鉴向、四倍频的原理以及使用EMPM7128S进行鉴向、四倍频、计数的方法，并给出了相应的VHDL程序和仿真图。
关键词：EPM7128S  鉴向  四倍频  VHDL

仿真时的波形

当A0A1=00,缓冲器buf_l,buf_m,buf_h不停的被刷新。到A0A1!=00时，缓冲器buf_l,buf_m,buf_h记录A0A1变化是的数据，A0A1=10  data=buf_l,
                  A0A1=11  data=buf_m,
                  A0A1=01  data=buf_h,


module AB4F(clk,a,b,cp,dire,data,a1,a0);
input clk,a,b,a1,a0;
output dire,cp;
reg        dire,cp;
reg [1:0]cot;
reg        [23:0] counter;
reg [1:0]prestate,state;
reg [7:0] buf_l,buf_m;
reg        [7:0] buf_h;
output [7:0]data;
reg [7:0]data;
always @(posedge clk)
begin
        state[1]<=a;
        state[0]<=b;
        prestate<=state;
        if((prestate==2'b00)&&(state==2'b10))
        begin
                cp<=1;dire<=1;
        end
        else if((prestate==2'b10)&&(state==2'b11))
        begin
                cp<=1;dire<=1;
        end
        else if((prestate==2'b11)&&(state==2'b01))
        begin
                cp<=1;dire<=1;
        end
        else if((prestate==2'b01)&&(state==2'b00))
        begin
                cp<=1;dire<=1;
        end
        else if((prestate==2'b00)&&(state==2'b01))
        begin
                cp<=1;dire<=0;
        end
        else if((prestate==2'b01)&&(state==2'b11))
        begin
                cp<=1;dire<=0;
        end
        else if((prestate==2'b11)&&(state==2'b10))
        begin
                cp<=1;dire<=0;
        end
        else if((prestate==2'b10)&&(state==2'b00))
        begin
                cp<=1;dire<=0;
        end
        else 
        begin
                if(cp)
                begin
                        cot<=cot+1;
                        if(cot==1)
                        begin
                                cot<=0;
                                cp<=0;
                        end
                end
        end        
end 
always @(negedge cp)
begin
        if(dire)
                begin
                        counter<=counter+1;
                end
        else
                begin
                        counter<=counter-1;
                end
end

always @(posedge clk)
         begin
                case({a1,a0})
         3'b00:
                        begin
                        buf_h<=counter[23:16];
                        buf_m<=counter[15:8];
                        buf_l<=counter[7:0];
                                data<=8'hzz;
                        end
         3'b01:data=buf_l;
         3'b11:data=buf_m;
         3'b10:data=buf_h;
        /*default:
                        begin
                        end*/
                endcase
end   endmodule 

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