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1。需要Design Linking license，ISE安装时自带了。
2。license许可控制在pci32_top.vhd文件中的298行--322行，我们去掉下面这些行，ise就不会检查license类型直接生成购买版的全功能core了。
3。pci32_top.vhd这个文件是加密的，所以你没办法修改。不要问我怎么打开的。直接看附件。pci32_top.nfo文件是改过的文件，使用时改扩展名.vhd。
---------------------------------------------------------------------------
-- IP licensing section
---------------------------------------------------------------------------
attribute check_license : string;
attribute check_license of pci32_top : entity is "pci32_v4";
--xlpp license_switch pci32_v4 begin
--xlpp simulation_license begin
attribute secure_bitstream : string;
attribute secure_bitstream of pci32_top : entity is "prohibit";
attribute secure_config : string;
attribute secure_config of pci32_top : entity is "protect";
attribute secure_netlist : string;
attribute secure_netlist of pci32_top : entity is "enable_unisim_hdl";
-- xlpp simulation_license end
-- xlpp eval_license begin
-- xlpp eval_license end
-- xlpp bought_license begin
-- xlpp bought_license end
-- xlpp license_switch end
4。用下面内容存成pci32_top.vhd，替换Xilinx\10.1\ISE\coregen\ip\xilinx\network\com\xilinx\ip\pci32_v4_6\pci32_top.vhd。执行Coregen，原来的警告不要管，实际就可以生成我们订制的PCI core了
pci32_top.vhd
--------------------------------------------------------------------------------
--
-- PCI Top Level File
--
--------------------------------------------------------------------------------
--
-- Copyright (c) 2005-2008 by Xilinx, Inc. All rights reserved.
-- This text/file contains proprietary, confidential
-- information of Xilinx, Inc., is distributed under
-- license from Xilinx, Inc., and may be used, copied
-- and/or disclosed only pursuant to the terms of a valid
-- license agreement with Xilinx, Inc. Xilinx hereby
-- grants you a license to use this text/file solely for
-- design, simulation, implementation and creation of
-- design files limited to Xilinx devices or technologies.
-- Use with non-Xilinx devices or technologies is expressly
-- prohibited and immediately terminates your license unless
-- covered by a separate agreement.
--
-- Xilinx is providing this design, code, or information
-- "as-is" solely for use in developing programs and
-- solutions for Xilinx devices, with no obligation on the
-- part of Xilinx to provide support. By providing this design,
-- code, or information as one possible implementation of
-- this feature, application or standard, Xilinx is making no
-- representation that this implementation is free from any
-- claims of infringement. You are responsible for obtaining
-- any rights you may require for your implementation.
-- Xilinx expressly disclaims any warranty whatsoever with
-- respect to the adequacy of the implementation, including
-- but not limited to any warranties or representations that this
-- implementation is free from claims of infringement, implied
-- warranties of merchantability or fitness for a particular
-- purpose.
--
-- Xilinx products are not intended for use in life support
-- appliances, devices, or systems. Use in such applications is
-- expressly prohibited.
--
-- Any modifications that are made to the Source Code are
-- done at the user's sole risk and will be unsupported.
-- The Xilinx Support Hotline does not have access to source
-- code and therefore cannot answer specific questions related
-- to source HDL. The Xilinx Hotline support of original source
-- code IP shall only address issues and questions related
-- to the standard Netlist version of the core (and thus
-- indirectly, the original core source).
--
-- This copyright and support notice must be retained as part
-- of this text at all times. Copyright (c) 1995-2008 Xilinx, Inc.
-- All rights reserved.
--
--------------------------------------------------------------------------------
--
-- Filename: pci32_top.vhd
--
-- Description:
-- Instantiated by the pci32_v4_6 top-level coregen wrapper, this wrapper
-- uses the pci32_pkg to convert incoming parameters to the PCI32 CFG bus
--
--------------------------------------------------------------------------------
-- Structure:
-- pci32_v4_6
-- |
-- +--pci32_top
-- |
-- +--pci_core (netlist)
-- |
-- +--pci32_pkg
--
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
-- LIBRARY DECLARATIONS
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library pci32_v4_6;
use pci32_v4_6.pci32_pkg.all;
entity pci32_top is
GENERIC (
-- PCI32 32/64-bit selection
-- This is here (in PCI32) for the later possibility that 32/64 may
-- be combined in one GUI. But this would require 2 licenses for 1
-- GUI, based on the width selection, which is not currently supported.
C_BUS_WIDTH : integer := 32; -- 32 is valid
-- PCI CFG bus width (will probably always be 512 - maybe unnecessary)
C_PCI_CFG_WIDTH : integer := 512;
-- ID values group
C_VENDOR_ID : string := "10ee";
C_DEVICE_ID : string := "0050";
C_REVISION_ID : string := "00";
C_SUBVENDOR_ID : string := "10ee";
C_SUBDEVICE_ID : string := "0050";
-- Optional capability register
C_USERCAP_ENABLED : integer := 0;
C_USERCAP_ADDR : string := "00";
-- Class Code group
C_BASE_CLASS : string := "00";
C_SUB_CLASS : string := "00";
C_SW_INTERFACE : string := "00";
C_CLASS_CODE : string := "000000";
-- Cardbus CIS pointer group
C_CARDBUS_CIS : string := "00000000";
-- Arbitration settings group
C_MAX_LAT : string := "00";
C_MIN_GNT : string := "00";
-- Base address register groups
-- BAR 0
C_BAR0_ENABLED : integer := 0;
C_BAR0_WIDTH : integer := 0;
C_BAR0_SIZE : integer := 0;
C_BAR0_SCALE : integer := 0;
C_BAR0_TYPE : integer := 0;
C_BAR0_PREFETCHABLE : integer := 0;
C_BAR0_VALUE : string := "00000000";
-- BAR 1
C_BAR1_ENABLED : integer := 0;
C_BAR1_WIDTH : integer := 0;
C_BAR1_SIZE : integer := 0;
C_BAR1_SCALE : integer := 0;
C_BAR1_TYPE : integer := 0;
C_BAR1_PREFETCHABLE : integer := 0;
C_BAR1_VALUE : string := "00000000";
-- BAR 2
C_BAR2_ENABLED : integer := 0;
C_BAR2_WIDTH : integer := 0;
C_BAR2_SIZE : integer := 0;
C_BAR2_SCALE : integer := 0;
C_BAR2_TYPE : integer := 0;
C_BAR2_PREFETCHABLE : integer := 0;
C_BAR2_VALUE : string := "00000000";
-- Implement group
C_IMPLEMENT_PCIX133 : integer := 0;
C_IMPLEMENT_PCIX66 : integer := 0;
C_IMPLEMENT_PCI66 : integer := 0;
C_IMPLEMENT_PCI33 : integer := 0;
-- Implement group
C_REVERSE_PINOUT : integer := 0;
-- Clock Type group
C_CLOCK_TYPE : integer := 0
);
PORT (
ADO : out std_logic_vector(C_BUS_WIDTH-1 downto 0);
ADI : in std_logic_vector(C_BUS_WIDTH-1 downto 0);
ADD : in std_logic_vector(C_BUS_WIDTH-1 downto 0);
ADT : out std_logic_vector(C_BUS_WIDTH-1 downto 0);
CBO : out std_logic_vector((C_BUS_WIDTH/8)-1 downto 0);
CBI : in std_logic_vector((C_BUS_WIDTH/8)-1 downto 0);
CBD : in std_logic_vector((C_BUS_WIDTH/8)-1 downto 0);
CBT : out std_logic_vector((C_BUS_WIDTH/8)-1 downto 0);
PARO : out std_logic;
PARI : in std_logic;
PARD : in std_logic;
PART : out std_logic;
PAR64O : out std_logic;
PAR64I : in std_logic;
PAR64D : in std_logic;
PAR64T : out std_logic;
FRAMEO : out std_logic;
FRAMEI : in std_logic;
FRAMED : in std_logic;
FRAMET : out std_logic;
REQ64O : out std_logic;
REQ64I : in std_logic;
REQ64D : in std_logic;
REQ64T : out std_logic;
TRDYO : out std_logic;
TRDYI : in std_logic;
TRDYD : in std_logic;
TRDYT : out std_logic;
IRDYO : out std_logic;
IRDYI : in std_logic;
IRDYD : in std_logic;
IRDYT : out std_logic;
STOPO : out std_logic;
STOPI : in std_logic;
STOPD : in std_logic;
STOPT : out std_logic;
DEVSELO : out std_logic;
DEVSELI : in std_logic;
DEVSELD : in std_logic;
DEVSELT : out std_logic;
ACK64O : out std_logic;
ACK64I : in std_logic;
ACK64D : in std_logic;
ACK64T : out std_logic;
PERRO : out std_logic;
PERRI : in std_logic;
PERRD : in std_logic;
PERRT : out std_logic;
SERRO : out std_logic;
SERRI : in std_logic;
SERRD : in std_logic;
SERRT : out std_logic;
INTO : out std_logic;
INTT : out std_logic;
PMEO : out std_logic;
PMET : out std_logic;
REQO : out std_logic;
REQT : out std_logic;
GNTI : in std_logic;
GNTD : in std_logic;
IDSELI : in std_logic;
IDSELD : in std_logic;
FRAMEQ_N : out std_logic;
REQ64Q_N : out std_logic;
TRDYQ_N : out std_logic;
IRDYQ_N : out std_logic;
STOPQ_N : out std_logic;
DEVSELQ_N : out std_logic;
ACK64Q_N : out std_logic;
ADDR : out std_logic_vector(31 downto 0);
ADIO_IN : in std_logic_vector(C_BUS_WIDTH-1 downto 0);
ADIO_OUT : out std_logic_vector(C_BUS_WIDTH-1 downto 0);
CFG_VLD : out std_logic;
CFG_HIT : out std_logic;
C_TERM : in std_logic;
C_READY : in std_logic;
ADDR_VLD : out std_logic;
BASE_HIT : out std_logic_vector(7 downto 0);
S_CYCLE64 : out std_logic;
S_TERM : in std_logic;
S_READY : in std_logic;
S_ABORT : in std_logic;
S_WRDN : out std_logic;
S_SRC_EN : out std_logic;
S_DATA_VLD : out std_logic;
S_CBE : out std_logic_vector((C_BUS_WIDTH/8)-1 downto 0);
PCI_CMD : out std_logic_vector(15 downto 0);
REQUEST : in std_logic;
REQUEST64 : in std_logic;
REQUESTHOLD : in std_logic;
COMPLETE : in std_logic;
M_WRDN : in std_logic;
M_READY : in std_logic;
M_SRC_EN : out std_logic;
M_DATA_VLD : out std_logic;
M_CBE : in std_logic_vector((C_BUS_WIDTH/8)-1 downto 0);
TIME_OUT : out std_logic;
M_FAIL64 : out std_logic;
CFG_SELF : in std_logic;
M_DATA : out std_logic;
DR_BUS : out std_logic;
I_IDLE : out std_logic;
M_ADDR_N : out std_logic;
IDLE : out std_logic;
B_BUSY : out std_logic;
S_DATA : out std_logic;
BACKOFF : out std_logic;
INT_N : in std_logic;
PME_N : in std_logic;
PERRQ_N : out std_logic;
SERRQ_N : out std_logic;
KEEPOUT : in std_logic;
CSR : out std_logic_vector(39 downto 0);
PCIW_EN : out std_logic;
BW_DETECT_DIS : in std_logic;
BW_MANUAL_32B : in std_logic;
PCIX_EN : out std_logic;
BM_DETECT_DIS : in std_logic;
BM_MANUAL_PCI : in std_logic;
RTR : out std_logic;
RST : in std_logic;
CFG : out std_logic_vector(511 downto 0);
CLK : in std_logic
);
---------------------------------------------------------------------------
-- X_CORE_INFO section
---------------------------------------------------------------------------
attribute X_CORE_INFO : string;
attribute X_CORE_INFO of pci32_top : entity is "pci32_v4_6, Coregen 10.1i_ip0";
end pci32_top;
architecture xilinx of pci32_top IS
-- Generate the CFG bus from the GUI parameters
-------------------------------------------------
constant cfgbus : std_logic_vector (511 downto 0) :=
param_to_pci_cfg(C_BUS_WIDTH,
C_BAR0_VALUE,
C_BAR0_WIDTH,
C_BAR1_VALUE,
C_BAR1_WIDTH,
C_BAR2_VALUE,
C_BAR2_WIDTH,
C_CARDBUS_CIS,
C_CLASS_CODE,
C_DEVICE_ID,
C_IMPLEMENT_PCI66,
C_MAX_LAT,
C_MIN_GNT,
C_REVISION_ID,
C_SUBDEVICE_ID,
C_SUBVENDOR_ID,
C_USERCAP_ADDR,
C_USERCAP_ENABLED,
C_VENDOR_ID
);
-- This is the core netlist
component pci_core is
port (
ADO : out std_logic_vector(C_BUS_WIDTH-1 downto 0);
ADI : in std_logic_vector(63 downto 0);
ADD : in std_logic_vector(63 downto 0);
ADT : out std_logic_vector(C_BUS_WIDTH-1 downto 0);
CBO : out std_logic_vector((C_BUS_WIDTH/8)-1 downto 0);
CBI : in std_logic_vector(7 downto 0);
CBD : in std_logic_vector(7 downto 0);
CBT : out std_logic_vector((C_BUS_WIDTH/8)-1 downto 0);
PARO : out std_logic;
PARI : in std_logic;
PARD : in std_logic;
PART : out std_logic;
PAR64O : out std_logic;
PAR64I : in std_logic;
PAR64D : in std_logic;
PAR64T : out std_logic;
FRAMEO : out std_logic;
FRAMEI : in std_logic;
FRAMED : in std_logic;
FRAMET : out std_logic;
REQ64O : out std_logic;
REQ64I : in std_logic;
REQ64D : in std_logic;
REQ64T : out std_logic;
TRDYO : out std_logic;
TRDYI : in std_logic;
TRDYD : in std_logic;
TRDYT : out std_logic;
IRDYO : out std_logic;
IRDYI : in std_logic;
IRDYD : in std_logic;
IRDYT : out std_logic;
STOPO : out std_logic;
STOPI : in std_logic;
STOPD : in std_logic;
STOPT : out std_logic;
DEVSELO : out std_logic;
DEVSELI : in std_logic;
DEVSELD : in std_logic;
DEVSELT : out std_logic;
ACK64O : out std_logic;
ACK64I : in std_logic;
ACK64D : in std_logic;
ACK64T : out std_logic;
PERRO : out std_logic;
PERRI : in std_logic;
PERRD : in std_logic;
PERRT : out std_logic;
SERRO : out std_logic;
SERRI : in std_logic;
SERRD : in std_logic;
SERRT : out std_logic;
INTO : out std_logic;
INTT : out std_logic;
PMEO : out std_logic;
PMET : out std_logic;
REQO : out std_logic;
REQT : out std_logic;
GNTI : in std_logic;
GNTD : in std_logic;
IDSELI : in std_logic;
IDSELD : in std_logic;
FRAMEQ_N : out std_logic;
REQ64Q_N : out std_logic;
TRDYQ_N : out std_logic;
IRDYQ_N : out std_logic;
STOPQ_N : out std_logic;
DEVSELQ_N : out std_logic;
ACK64Q_N : out std_logic;
ADDR : out std_logic_vector(31 downto 0);
ADIO_IN : in std_logic_vector(63 downto 0);
ADIO_OUT : out std_logic_vector(C_BUS_WIDTH-1 downto 0);
CFG_VLD : out std_logic;
CFG_HIT : out std_logic;
C_TERM : in std_logic;
C_READY : in std_logic;
ADDR_VLD : out std_logic;
BASE_HIT : out std_logic_vector(7 downto 0);
S_CYCLE64 : out std_logic;
S_TERM : in std_logic;
S_READY : in std_logic;
S_ABORT : in std_logic;
S_WRDN : out std_logic;
S_SRC_EN : out std_logic;
S_DATA_VLD : out std_logic;
S_CBE : out std_logic_vector((C_BUS_WIDTH/8)-1 downto 0);
PCI_CMD : out std_logic_vector(15 downto 0);
REQUEST : in std_logic;
REQUEST64 : in std_logic;
REQUESTHOLD : in std_logic;
COMPLETE : in std_logic;
M_WRDN : in std_logic;
M_READY : in std_logic;
M_SRC_EN : out std_logic;
M_DATA_VLD : out std_logic;
M_CBE : in std_logic_vector(7 downto 0);
TIME_OUT : out std_logic;
M_FAIL64 : out std_logic;
CFG_SELF : in std_logic;
M_DATA : out std_logic;
DR_BUS : out std_logic;
I_IDLE : out std_logic;
M_ADDR_N : out std_logic;
IDLE : out std_logic;
B_BUSY : out std_logic;
S_DATA : out std_logic;
BACKOFF : out std_logic;
INT_N : in std_logic;
PME_N : in std_logic;
PERRQ_N : out std_logic;
SERRQ_N : out std_logic;
KEEPOUT : in std_logic;
CSR : out std_logic_vector(39 downto 0);
PCIW_EN : out std_logic;
BW_DETECT_DIS : in std_logic;
BW_MANUAL_32B : in std_logic;
PCIX_EN : out std_logic;
BM_DETECT_DIS : in std_logic;
BM_MANUAL_PCI : in std_logic;
RTR : out std_logic;
RST : in std_logic;
CFG : in std_logic_vector(511 downto 0);
CLK : in std_logic
);
end component;
attribute box_type: string;
attribute box_type of pci_core: component is "black_box";
signal ff_drive_zero_1 : std_logic;
constant ff_drive_zero_4 : std_logic_vector(3 downto 0) := X"0";
constant ff_drive_zero_32 : std_logic_vector(31 downto 0) := X"00000000";
signal core_ADI : std_logic_vector(63 downto 0);
signal core_ADD : std_logic_vector(63 downto 0);
signal core_CBI : std_logic_vector(7 downto 0);
signal core_CBD : std_logic_vector(7 downto 0);
signal core_ADIO_IN : std_logic_vector(63 downto 0);
signal core_M_CBE : std_logic_vector(7 downto 0);
begin
-- These pins are 64-bit only inputs, so in the 32-bit wrapper
-- they must be driven by a FF so they are not trimmed
-- PAR64I
-- REQ64I
-- ACK64I
-- REQUEST64
process (CLK, RST)
begin
if (CLK='1' and CLK'event) then
if (RST='1') then
ff_drive_zero_1 <= '1';
-- ff_drive_zero_4 <= x"f";
-- ff_drive_zero_32 <= x"ffffffff";
else
ff_drive_zero_1 <= '0';
-- ff_drive_zero_4 <= x"0";
-- ff_drive_zero_32 <= x"00000000";
end if;
end if;
end process;
pad_32_bit_signals: if (C_BUS_WIDTH = 32) generate
core_ADI <= ff_drive_zero_32 & ADI;
core_ADD <= ff_drive_zero_32 & ADD;
core_CBI <= ff_drive_zero_4 & CBI;
core_CBD <= ff_drive_zero_4 & CBD;
core_ADIO_IN <= ff_drive_zero_32 & ADIO_IN;
core_M_CBE <= ff_drive_zero_4 & M_CBE;
end generate;
pass_64_bit_signals: if (C_BUS_WIDTH = 64) generate
core_ADI <= ADI;
core_ADD <= ADD;
core_CBI <= CBI;
core_CBD <= CBD;
core_ADIO_IN <= ADIO_IN;
core_M_CBE <= M_CBE;
end generate;
pci32_inst : pci_core
PORT MAP (
ADO => ADO,
ADI => core_ADI,
ADD => core_ADD,
ADT => ADT,
CBO => CBO,
CBI => core_CBI,
CBD => core_CBD,
CBT => CBT,
PARO => PARO,
PARI => PARI,
PARD => PARD,
PART => PART,
PAR64O => PAR64O,
PAR64I => ff_drive_zero_1,
PAR64D => ff_drive_zero_1,
PAR64T => PAR64T,
FRAMEO => FRAMEO,
FRAMEI => FRAMEI,
FRAMED => FRAMED,
FRAMET => FRAMET,
REQ64O => REQ64O,
REQ64I => ff_drive_zero_1,
REQ64D => ff_drive_zero_1,
REQ64T => REQ64T,
TRDYO => TRDYO,
TRDYI => TRDYI,
TRDYD => TRDYD,
TRDYT => TRDYT,
IRDYO => IRDYO,
IRDYI => IRDYI,
IRDYD => IRDYD,
IRDYT => IRDYT,
STOPO => STOPO,
STOPI => STOPI,
STOPD => STOPD,
STOPT => STOPT,
DEVSELO => DEVSELO,
DEVSELI => DEVSELI,
DEVSELD => DEVSELD,
DEVSELT => DEVSELT,
ACK64O => ACK64O,
ACK64I => ff_drive_zero_1,
ACK64D => ff_drive_zero_1,
ACK64T => ACK64T,
PERRO => PERRO,
PERRI => PERRI,
PERRD => PERRD,
PERRT => PERRT,
SERRO => SERRO,
SERRI => SERRI,
SERRD => SERRD,
SERRT => SERRT,
INTO => INTO,
INTT => INTT,
PMEO => PMEO,
PMET => PMET,
REQO => REQO,
REQT => REQT,
GNTI => GNTI,
GNTD => GNTD,
IDSELI => IDSELI,
IDSELD => IDSELD,
FRAMEQ_N => FRAMEQ_N,
REQ64Q_N => REQ64Q_N,
TRDYQ_N => TRDYQ_N,
IRDYQ_N => IRDYQ_N,
STOPQ_N => STOPQ_N,
DEVSELQ_N => DEVSELQ_N,
ACK64Q_N => ACK64Q_N,
ADDR => ADDR,
ADIO_IN => core_ADIO_IN,
ADIO_OUT => ADIO_OUT,
CFG_VLD => CFG_VLD,
CFG_HIT => CFG_HIT,
C_TERM => C_TERM,
C_READY => C_READY,
ADDR_VLD => ADDR_VLD,
BASE_HIT => BASE_HIT,
S_CYCLE64 => S_CYCLE64,
S_TERM => S_TERM,
S_READY => S_READY,
S_ABORT => S_ABORT,
S_WRDN => S_WRDN,
S_SRC_EN => S_SRC_EN,
S_DATA_VLD => S_DATA_VLD,
S_CBE => S_CBE,
PCI_CMD => PCI_CMD,
REQUEST => REQUEST,
REQUEST64 => ff_drive_zero_1,
REQUESTHOLD => REQUESTHOLD,
COMPLETE => COMPLETE,
M_WRDN => M_WRDN,
M_READY => M_READY,
M_SRC_EN => M_SRC_EN,
M_DATA_VLD => M_DATA_VLD,
M_CBE => core_M_CBE,
TIME_OUT => TIME_OUT,
M_FAIL64 => M_FAIL64,
CFG_SELF => CFG_SELF,
M_DATA => M_DATA,
DR_BUS => DR_BUS,
I_IDLE => I_IDLE,
M_ADDR_N => M_ADDR_N,
IDLE => IDLE,
B_BUSY => B_BUSY,
S_DATA => S_DATA,
BACKOFF => BACKOFF,
INT_N => INT_N,
PME_N => PME_N,
PERRQ_N => PERRQ_N,
SERRQ_N => SERRQ_N,
KEEPOUT => KEEPOUT,
CSR => CSR,
PCIW_EN => PCIW_EN,
BW_DETECT_DIS => BW_DETECT_DIS,
BW_MANUAL_32B => BW_MANUAL_32B,
PCIX_EN => PCIX_EN,
BM_DETECT_DIS => BM_DETECT_DIS,
BM_MANUAL_PCI => BM_MANUAL_PCI,
RTR => RTR,
CFG => cfgbus,
RST => RST,
CLK => CLK
);
-- Assign the CoreGen created cfgbus to the CFG output
CFG <= cfgbus;
end xilinx;
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