详细说明：DDR RAM控制器的VHDL源码，实现平台是Lattice FPGA，功能验证通过-DDR RAM controller VHDL source code, achieving the platform of Lattice FPGA, functional verification through

文件列表:

  rd1020_DDR SDRAM Controller

  ...........................\DDR SDRAM Controller.files

  ...........................\..........................\arrow.gif

  ...........................\..........................\arrow1.gif

  ...........................\..........................\ddr_controller.gif

  ...........................\..........................\external.css

  ...........................\..........................\footer.gif

  ...........................\..........................\go.gif

  ...........................\..........................\header.gif

  ...........................\..........................\make_agent_emb.jpg

  ...........................\..........................\pdfmid.gif

  ...........................\..........................\ref_design_logo.gif

  ...........................\rd1020.pdf

  ...........................\source

  ...........................\......\ddr_ctrl.v

  ...........................\......\ddr_data.v

  ...........................\......\ddr_par.v

  ...........................\......\ddr_pll_orca.v

  ...........................\......\ddr_pll_orca_sp.v

  ...........................\......\ddr_sig.v

  ...........................\......\ddr_top.v

  ...........................\testbench

  ...........................\.........\ddr_tb.v

  ...........................\.........\stimulus.v