Xilinx Customer Education
Instructor Notes

Course: Designing for Performance

Notes about this course

·          This course is intermediate level and can follow the one-day Fundamentals of FPGA Design course, to create a three-day training suite.

·          The Synthesis Techniques module refers to Synopsys FPGA Compiler II, Exemplar LeonardoSpectrum, Synplicity Synplify, and Xilinx XST. The Synthesis Techniques lab is available for LeonardoSpectrum, Synplify Pro, and XST.  

·          Some of the modules include software demonstrations (CORE Generator System, XPower, and Timing Groups and OFFSET Constraints).  You should guide the students through the demonstration.  Each demo is described in the Notes portion of the slides.

o         We encourage you to use a demonstration any time that you feel doing so will increase the learning experience.  However, you should run through any demo you wish to use before doing running through the demo in front of the students, so you know what to expect.  Use one of the projects from the training\desperf\lab directory to be certain the students will obtain results similar to yours.

o         When a Where Can I Learn More? slide contains Web references, feel free to perform a guided tour demo: http://support.xilinx.com

·          This slide show contains slides with review questions followed by slides containing the answers.

·          Workbooks are printed in PowerPoint Notes view. The slides include notes for both instructor and student.

·          Throughout the course, stress the steps students should take before attempting the next step.  For example, before going through the Synthesis Techniques section, question the students about which steps should have been completed previously: Behavioral simulation, correct coding techniques for high speed (use Case statements, use one-hot selects, pipeline, etc.), and synchronous design techniques.

·          There are several additional sections in the back of the book: Glossary of Terms, Troubleshooting Tips, and FPGA Design Checklist.  Point these out to the students.

o         Glossary: Definitions of acronyms and general industry terminology.

o         Troubleshooting Tips: Several key mistakes/problems that designers often overlook in their designs.

o         FPGA Design Checklist: Checklist on specific techniques that help make a design faster and more reliable.

·          Labs:

o         Run through the labs yourself before teaching the class.  You should be aware of any specific problems/questions the students may encounter.  You may need to clarify some steps or information about the lab.

o         Each lab now consists of 3 sections:

§          The first section is a PowerPoint slide set that introduces the lab.  It briefly describes the lab objectives, lab design, and the steps students will take.

§          The second section is the actual lab script, which the students will follow to perform the lab.  There has been a change to the lab format, allowing experienced students to follow general instructions, while still providing step-by-step instruction for novice students.  Lab answers no longer contain specific numbers for performance or Timing Score.  During the lab wrap-up, confirm that students are seeing performance improvement.

§          The third section is a PowerPoint slide set that reviews the lab.  It contains some open-ended review questions that are intended to stimulate discussion.  No answers are provided.

o         The first lab, on day one, is a set of written exercises.  To manage class time, limit the amount of time the students spend on each code fragment to 5 minutes, then discuss the coding style concept as a group for 5 minutes before moving on to the next code fragment.

o         The final lab, on day two, combines all of the concepts of obtaining performance objectives with the use of constraints.  Ensure that you understand the specifics of the constraints that are used (especially the ones in finished_UCF.txt).  For additional information on these constraints contact Rhett Whatcott (Rhett.Whatcott@xilinx.com (801) 773-9890).

Sample Agenda

Day 1

Course Introduction/Agenda                      9:00 – 9:30

Review of Fundamentals                          9:30 – 9:45
Advanced Virtex II Architecture                 9:45 – 10:30

Break                                           10:30 – 10:45

FPGA Design Techniques                          10:45 – 11:30

HDL Coding Style                                11:30 – 12:00

Lunch                                           12:00 – 1:00

Lab #1: Coding Style                            1:00 – 1:45

Synthesis Techniques                            1:45 – 2:30

Lab #2: Synthesis Techniques                    2:30 – 3:15

Break                            3:15 – 3:30

CORE Generatorä System     3:30 – 4:15

Lab #3: CORE Generatorä System  4:15 – 5:00

Day 2

Agenda                      9:00 – 9:15

XPower                      9:15 – 10:00

Lab #4: Review of Global Constraints 10:00 – 10:45

Break                                           10:45 – 11:00

Achieving Timing Closure             11:00 – 12:00

Lunch                            12:00 – 1:00

Timing Groups and OFFSET Constraints1:00 – 1:45

Path-Specific Timing Constraints     1:45 – 2:30

Break                            2:30 – 2:45

Lab #5: Achieving Timing Closure     2:45 – 4:00

Advanced Implementation Options  4:00 – 4:45

Course Summary                   4:45 – 5:00

Teaching Activities

Structured Discussion           x

Paper exercise(s)               x

Lab exercise(s)                 x

Demo x

Review questions                x

Test

Labs & Lab Setup

There are five lab exercises associated with this course. All labs have been verified on desktop PCs running Windows 2000 with Service Pack 1 and the Xilinx software listed below.

Software and Hardware Requirements

Xilinx software: ISE 5 (no service packs)

Third-party software: Synplicity’s Synplify Pro 7.1, Exemplar’s Leonardo Spectrum 2002b, Xilinx XST 5, ModelSim SE 5.6b

Required device support: Virtex-II family (XC2V40 - XC2V250)

Lab Setup

The Companion CD contains the following files:

Read Me, Lab files, Slides

文件列表:

  desperf_readme.doc

  training

  ........\desperf

  ........\.......\labs

  ........\.......\....\coregen

  ........\.......\....\.......\verilog

  ........\.......\....\.......\.......\ch_fifo.v

  ........\.......\....\.......\.......\coregen_lab

  ........\.......\....\.......\.......\...........\automake.err

  ........\.......\....\.......\.......\...........\coregen_lab.npl

  ........\.......\....\.......\.......\...........\modelsim.ini

  ........\.......\....\.......\.......\...........\__projnav

  ........\.......\....\.......\.......\...........\.........\coregen_lab.gfl

  ........\.......\....\.......\.......\...........\__projnav.log

  ........\.......\....\.......\.......\correlate_and_accumulate.v

  ........\.......\....\.......\.......\data_control.v

  ........\.......\....\.......\.......\data_control_fsm.v

  ........\.......\....\.......\.......\data_output_mux.v

  ........\.......\....\.......\.......\fifo_2048x8.v

  ........\.......\....\.......\.......\fifo_2048x8_tb.tf

  ........\.......\....\.......\.......\fifo_status.v

  ........\.......\....\.......\.......\fifo_ver.do

  ........\.......\....\.......\.......\mac.v

  ........\.......\....\.......\.......\mac_ch.v

  ........\.......\....\.......\.......\pn_correlation.v

  ........\.......\....\.......\.......\pn_correlation_fsm.v

  ........\.......\....\.......\.......\pn_correlator.v

  ........\.......\....\.......\.......\read_ch_arbiter.v

  ........\.......\....\.......\vhdl

  ........\.......\....\.......\....\ch_fifo.vhd

  ........\.......\....\.......\....\coregen_lab

  ........\.......\....\.......\....\...........\automake.err

  ........\.......\....\.......\....\...........\coregen_lab.npl

  ........\.......\....\.......\....\...........\modelsim.ini

  ........\.......\....\.......\....\...........\__projnav

  ........\.......\....\.......\....\...........\.........\coregen_lab.gfl

  ........\.......\....\.......\....\...........\__projnav.log

  ........\.......\....\.......\....\correlate_and_accumulate.vhd

  ........\.......\....\.......\....\correlate_and_accumulate_pack.vhd

  ........\.......\....\.......\....\data_control.vhd

  ........\.......\....\.......\....\data_control_fsm.vhd

  ........\.......\....\.......\....\data_output_mux.vhd

  ........\.......\....\.......\....\fifo_2048x8.vhd

  ........\.......\....\.......\....\fifo_2048x8_tb.vhd

  ........\.......\....\.......\....\fifo_status.vhd

  ........\.......\....\.......\....\fifo_vhd.do

  ........\.......\....\.......\....\mac.vhd

  ........\.......\....\.......\....\mac_ch.vhd

  ........\.......\....\.......\....\pn_correlation.vhd

  ........\.......\....\.......\....\pn_correlation_fsm.vhd

  ........\.......\....\.......\....\pn_correlator.vhd

  ........\.......\....\.......\....\read_ch_arbiter.vhd

  ........\.......\....\synthesis

  ........\.......\....\.........\spectrum

  ........\.......\....\.........\........\verilog

  ........\.......\....\.........\........\.......\data_control.v

  ........\.......\....\.........\........\.......\data_control_fsm.v

  ........\.......\....\.........\........\.......\data_output_mux.v

  ........\.......\....\.........\........\.......\mac.v

  ........\.......\....\.........\........\.......\mac_ch.v

  ........\.......\....\.........\........\.......\read_ch_arbiter.v

  ........\.......\....\.........\........\.......\synth_lab

  ........\.......\....\.........\........\.......\.........\automake.err

  ........\.......\....\.........\........\.......\.........\synth_lab.npl

  ........\.......\....\.........\........\.......\.........\__projnav

  ........\.......\....\.........\........\.......\.........\.........\synth_lab.gfl

  ........\.......\....\.........\........\.......\.........\__projnav.log

  ........\.......\....\.........\........\vhdl

  ........\.......\....\.........\........\....\correlate_and_accumulate_pack.vhd

  ........\.......\....\.........\........\....\data_control.vhd

  ........\.......\....\.........\........\....\data_control_fsm.vhd

  ........\.......\....\.........\........\....\data_output_mux.vhd

  ... ...