There is much excitement in the design and verification

community about assertion-based design. The question is, who

should study assertion-based design? The emphatic answer is,

both design and verification engineers.

What may be unintuitive to many design engineers is that adding

assertions to RTL code will actually reduce design time, while

better documenting design intent.

Every design engineer should read this book! Design engineers

that add assertions to their design will not only reduce the time

needed to complete a design, they will also reduce the number of

interruptions from verification engineers to answer questions

about design intent and to address verification suite mistakes.

With design assertions in place, the majority of the interruptions

from verification engineers will be related to actual design

problems and the error feedback provided will be more useful to

help identify design flaws. A design engineer who does not add

assertions to the RTL code will spend more time with verification

engineers explaining the design functionality and intended

interface requirements, knowledge that is needed by the

verification engineer to complete the job of testing the design.

Every verification engineer should read this book! The smart

verification engineer will assist the design engineer to add

assertions to the RTL-design code because the sooner a design

engineer understands the usage and benefits of inserting assertions

into the design, the more valuable that design engineer will be to

the verification effort. A smart verification engineer is someone

who can help a designer to catch the vision and understand the

ease and value of assertion-based design. This is the first book to

comprehensively address and explain HDL assertion-based

design.

My colleague Harry Foster is the best-known name in the Verilog

verification and assertion-based methodology community. Along

with Lionel Bening, Harry pioneered the Verilog Open

Verification Library (OVL), a freely available set of verificationfocused

Verilog modules that have been used in advanced design

and verification environments ever since they were introduced.

My colleague Adam Krolnik was the verification champion of the

Verilog-2001 Standards Group. I counted on Adam to promote

Foreword xv

and propose verification enhancements to the IEEE Verilog

language.

David Lacey, Harry and Adam are key participants on the

Accellera SystemVerilog Standards Group. Their practical

verification experience has contributed to the value of the

assertion enhancements added to the SystemVerilog standard.

These three verification specialists have written a book that will

endow the reader with an understanding of the fundamental and

important topics needed to comprehend and implement assertionbased

design.

Included in Chapter 7 of this book is a valuable set of commonly

used assertion examples to help the reader become familiar with

the capabilities of assertion-based design. This book is a must for

all design and verification engineers.

Clifford E. Cummings

Verilog Guru & President, Sunburst Design, Inc.

Member IEEE 1364-1995 Verilog Standards Group

Member IEEE 1364-2001 Verilog Standards Group

Member IEEE 1364-2002 Verilog RTL Synthesis Standards Group

Member Accellera SystemVerilog 3.0 Standards Group

Member Accellera SystemVerilog 3.1 Standards Group