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Design For Test
运行环境: Win9x/NT/2000/XP/2003 文件大小: 703 K
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开 发 商: Free 软件语言: 英文
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Design For Test

About This Manual

This Design for Testability Reference Guide provides information on

developing test strategies for ASIC designs.

The following list summarizes the chapters of this ASIC document.

How to Use This Manual

The chapter highlights are presented in the following text.

Chapter 1 Introduction to Design for Testability

Introduces the subjects of designing for testability in the beginning of the

design process, fault simulation, and dc parametric testing

Chapter 2 Reasons for Using Design for Testability

Discusses the time and money savings achieved by using and integrating

design for testability (DFT) early in your design process. Discusses fault

grading and fault coverage.

Chapter 3 Developing a Testability Strategy

Presents strategies for developing testability techniques

Chapter 4 Test Pattern Requirements

Presents the required and optional TDL pattern types

Chapter 5 Ad Hoc Testability Practices

Recommends some work-arounds and techniques that are useful for

improving your testability

iv Design for Testability

How to Use This Manual

Chapter 6 Structured Testability Practices

Discusses the different types of scan design testing

Chapter 7 IEEE Standard 1149.1-1990

Provides an overview of the IEEE Std 1149.1 and gives an overview of the

boundary-scan architecture

Chapter 8 Generic Test Access Port

Discusses the generic test access port (GTAP), which is used to enable and

disable various DFT features

Chapter 9 Parallel Module Test

Presents information on parallel module test (PMT), how to use PMT with

MegaModules, such as howto test buses and hook up test buses to device pins

Chapter 10 Parametric Measurements

Discusses using parametric testing to guarantee conformance to electrical

data sheets and presents information on the use of boundary-scan, pattern

sets, and TDL types

Chapter 11 Automatic Test Pattern Generation

Presents automatic test pattern generation (ATPG) methodologies, such as

path sensitization and full and partial scan

Chapter 12 Test Pattern Generation

Discusses generating test patterns for use by automated test equipment (ATE)

Chapter 13 IEEE Standard 1149.1-Based dc Parametric Testing

Discusses what is required in performing IEEE Standard 1149.1-based dc

parametric testing

Chapter 14 Military ASIC

Summarizes military ASIC documents and the location of military-specific

design information

Appendix A Glossary

Contains important ASIC words, phrases, and software tools

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