Abstract: An approach is presented for minimizing power consumption for digital systems implemented

in CMOS which involves optimization at all levels of the design. This optimization includes the technology

used to implement the digital circuits, the circuit style and topology, the architecture for implementing

the circuits and at the highest level the algorithms that are being implemented. The most important

technology consideration is the threshold voltage and its control which allows the reduction of supply

voltage without significant impact on logic speed. Even further supply reductions can be made by the use

of an architecture based voltage scaling strategy, which uses parallelism and pipelining, to trade-off silicon

area and power reduction. Since energy is only consumed when capacitance is being switched,

power can be reduced by minimizing this capacitance through operation reduction, choice of number

representation, exploitation of signal correlations, re-synchronization to minimize glitching, logic design,

circuit design and physical design. The low-power techniques that are presented have been applied to the

design of a chipset for a portable multimedia terminal that supports pen input, speech I/O and fullmotion

video. The entire chipset that performs protocol conversion, synchronization, error correction,

packetization, buffering, video decompression and D/A conversion operates from a 1.1V supply and consumes

less than 5mW.