Chapter 3. Measurement Techniques 57
3-1 Switching Speed 57
3-2 Phase Noise 61
3-2-1 FM Noise 62
3-2-2 Delay Line Discriminator 63
3-2-3 Integrated Phase Noise 66
3-2-4 Noise Density 66
3-3 Phase Continuity 66
3-4 Spurious Signals (Especially DDS) 67
3-5 Phase Memory 69
3-6 Step Size 69
3-7 Linear FM 70
3-8 Conclusion 70
References 71
Chapter 4. DDS General Architecture 73
4-1 Digital Modulators and Signal Reconstruction 75
4-2 Pulse Output DDS of the First Order 82
4-3 Pulse Output DDS of the Second Order 87
4-4 Standard DDS 89
4-4-1 Binary-Coded Decimal DDS 100
4-5 Randomization 105
4-5-1 Wheatley Procedure 106
4-5-2 Randomizing Sine Output 108
4-6 Quantization Errors 109
4-6-1 Digitized Model 109
4-7 Logic Speed Considerations 120
4-8 Modulation 120
4-9 State-of-the-Art Components and Systems 128
4-9-1 Very High-Speed Direct Digital Synthesizer 128
4-9-2 Medium-Speed Direct Digital Synthesizer 129
4-10 Performance Evaluation 133
4-10-1 Switching Speed 133
4-10-2 Phase Noise 133
4-10-3 Spurious Signals 134
4-10-4 Phase Continuity 134
4-10-5 Resolution 134
4-11 Sample-and-Hold Devices 134
4-12 Single-Bit DDS Revisited 135
4-13 Arbitrary Waveform Generators 138
4-14 Digital Chirp DDS 140
4-15 Conclusion 140
Appendix 4A DDS Applications 141
Appendix 4B DDS—Spectra and the Time Domain 143
Appendix 4C Sampling Theorem 157
Appendix 4D The Effect of Phase Noise on Data Conversion Devices 159
References 160
Chapter 5. Phase-Locked Loop Synthesizers 163
5-1 Main Components of PLL Synthesis 164
5-1-1 Voltage Controlled Oscillators 165
5-1-2 Analog Phase Detector 168
5-1-3 Digital Phase Detector 1 172
5-1-4 Digital Phase Detector 2 175
5-1-5 Digital Phase Detector 3 176
5-1-6 Digital/Analog Phase Detector 4 177
5-1-7 Dividers 180
5-2 Performance Evaluation 184
5-2-1 Wireless PLL ASIC Configuration 198
5-3 Fractional-N Synthesizers 201
5-3-1 Fractional-N Synthesis of the First Order 204
5-3-2 Fractional-N Synthesis of the Second Order 216
5-4 Fractional-N Synthesis of the Third Order 220
5-5 DDS-Based PLL 224
5-5-1 Speed Up 226
5-6 Single-Chip PLL Synthesis 227
5-7 Conclusion 230
References 235
Chapter 6. Accumulators 237
6-1 Binary Accumulators 237
6-2 Decimal Accumulators 245
6-3 Interface to ROM 246
6-4 Accumulator DDS 248
6-5 Phase Adder and Accumulator Segmentation 248
6-6 Conclusion 250
References 250
Chapter 7. Lookup Table and Sine ROM Compression 251
7-1 ROM Algorithm 252
7-2 Quadrant Compression 256
7-3 Compression Principles 259
7-4 Direct Taylor Approximation 260
7-5 Hutchison Algorithm 262
7-6 Sunderland Algorithm 266
7-7 Variations and Randomization 269
7-8 Auxiliary Function ROM Approximation 271
7-8-1 Spurious Signal Analysis 274
7-9 Coordinate Transformation (CORDIC) 275
7-10 Other Methods 278
7-11 Conclusion 279
References 280
Chapter 8. Digital-to-Analog Converters 281
8-1 DAC Performance Evaluation 282
8-2 DAC Principles of Operation 285
8-3 DAC Parameters 292
8-3-1 Update Rate 292
8-3-2 Resolution 292
8-3-3 Logic Format 293
8-3-4 Setup-and-Hold Time 293
8-3-5 Rise, Fall, and Settling Times 293
8-3-6 Propagation Delay Time 294
8-3-7 Differential Linearity 294
8-3-8 Integral Nonlinearity 294
8-3-9 Monotonicity 295
8-3-10 Multiplying Bandwidth 295
8-3-11 Glitch Energy 295
8-3-12 Symmetry 296
8-4 State-of-the-Art DACs 296
8-4-1 Low-Speed Operation 296
8-4-2 Medium-Speed Operation 298
8-4-3 Very High-Speed Operation 298
8-4-4 Other Recommended DACs 299
8-5 Sine-Wave DAC 299
8-6 Multiplexing 299
References 303
Chapter 9. Synthesizers in Use and Reference Generators 305
9-1 Synthesizers in Use 305
9-1-1 Hewlett-Packard 3325B 306
9-1-2 Hewlett-Packard 8662A 307
9-1-3 Program Test Sources 310 307
9-1-4 Comstron/Aeroflex FS-2000 309
9-1-5 Schomandl Models ND500 and ND1000 309
9-1-6 Stanford Research DS345 309
9-2 Reference Generators 313
9-2-1 General Review 314
9-2-2 Crystal Oscillators 316
9-3 Conclusion 319
References 319
Chapter 10. Original Paper and Software 321
10-1 Tierney, Rader, and Gold Article 321
10-2 Software Description 322
