PLL Frequency Synthesizers
Contents:
Index ii
List of figures v
List of Tables viii
List of symbols and abbreviations ix
Preface xiv
1. Introduction 1
1.1. The frontend in a telecommunication receiver 2
1.2. The frontend in TV broadcasting 3
1.3. Current tendencies: low noise and higher integration 9
1.4. PLL systems : different application contexts 14
1.5. PLL frequency synthesizers constituting blocks and nomenclature 15
1.5.1. VCO 16
1.5.2. Dividers 17
1.5.3. Phase Detector – Charge Pump 17
1.5.4. Loop Filter 19
2. PLL Phase Model and Loop Filter calculation 21
2.1. Phase Model for PLL synthesizers 22
2.1.1. Requirements in the Time and Frequency Domain 24
2.1.2. Second-Order Loop 26
2.1.3. Third and Fourth Order Loop 28
2.2. Algorithm for Loop Filter Calculation 34
2.2.1. Nominal Design 34
2.2.2. Robust design including Gain Variation and 3rd Pole compensation 36
2.2.3. Summary steps and numerical example 40
3. Application Related Constraints 43
3.1. Reference Breakthrough 44
3.2. VCO Noise Representation and Phase Noise Units 46
3.3. Optimum Closed Loop Bandwidth 50
3.4. PLL Closed Loop Bandwidth 52
3.4.1. w3dB derivation from BRL(s) 53
3.4.2. w3dB derivation from was 59
3.5. Maximum Phase Jitter 61
3.6. Gain Stability Boundary 65
4. Active Loop Filters: AC & disturbances issues 69
4.1. Non-ideal Filter Impedances 70
4.1.1. Fully 3rd order passive filter 71
4.1.2. Amplifier AC characteristics 72
4.1.3. Amplifier with single pole 74
4.1.4. Numerical example 76
4.1.5. Input impedance: Zin 79
4.1.6. Summary of AC boundaries for filter design 80
4.2. Disturbances and Noise Propagation 80
4.2.1. Random Electrical Noise 81
4.2.2. Supply Disturbances 82
4.2.3. Amplifier Noise 82
4.2.4. Filter Components Noise 83
4.2.5. Transfer functions table 84
4.2.6. Simulation Example 85
5. Limitations of the LTI Phase Model 89
5.1. Three-state comparator: frequency and phase detector 91
5.1.1. Minimum phase deviation range 92
5.2. DC range limitations 94
5.2.1. Loop filter time domain response 94
5.2.2. Numerical examples and design considerations 96
5.3. Lock convergency approaches 99
5.3.1. Frequency approach 100
5.3.2. Phase approach 103
5.3.3. Comparing the frequency and phase approaches: 105
5.4. Discrete trasfers for the PLL Phase Model 109
5.4.1. The sampler 109
5.4.2. The holder 111
5.4.3. Continuous equivalent with transmission delay 114
6. Phase Noise: theoretical to practical approach 119
6.1. Electrical Noise: random sources representation & measurements 120
6.1.1. Electrical noise as a random process 121
6.1.2. Measuring Phase Noise 123
6.2. Phase Noise Notations 125
6.2.1. Interchanging Modulation Types 125
6.2.1.1. Angular modulation 127
6.2.2. Phasors Notations 128
6.2.3. Slope approach 133
6.3. Large Signal Linearization 135
6.3.1. Time and Frequency representation 135
6.3.2. Linear Time Variable transfer 136
7. Phase Noise in the PLL context 141
7.1. Translating the SNF into phase, time, voltage and current noise 143
7.2. Sampling effects: SNF x fcp 147
7.2.1. Narrow bandwidth noise sources 149
7.2.2. Large bandwidth noise sources 151
7.3. Detailing noise sources in different PLL blocks 154
7.3.1. D-flip flop 154
7.3.2. Charge Pump 158
7.4. Behavioural Models 159
7.4.1. Frequency domain 159
7.4.2. Time domain 160
7.5. Implementation Loss due to Phase Deviations 162
7.5.1. Signal to noise ratio and implementation loss 163
7.5.2. Digital Demodulator: clock and carrier recovery loops 167
8. Testchips Realized 169
8.1. Gm-C oscillator 170
8.1.1. Structure 171
8.1.2. Results 172
8.2. TC2 : Mixer-Oscillator-PLL circuit for satellite direct conversion 173
8.2.1. Double Loop Synthesizer 173
8.2.2. TC2 structure 175
8.2.3. TC2: results 177
8.3. TC3 : single PLL plus QCCO circuit 180
8.4. Comparative analysis: phase jitter and implementation loss 183
8.4.1. Configurations compared 183
8.4.2. Conditions for the simulations 184
8.4.3. Results and conclusions 187
9. Conclusion 191
Bibliography 193 |
