Cmos Integrated Analog-To-Digital and Digital-To-Analog Converters (2nd edition)
Author: Rudy J. Van De Plassche
Format: Book, 640 pages, scanned
Publication Date: August 2003
Publisher: Kluwer Academic Pub
Dimensions:9.5"H x 6.25"W x 1"D; 2.75 lbs.
ISBN: 1402075006
List Price: $135.00
Editorial Reviews
Book Description
Analog-to-digital (A/D) and digital-to-analog (D/A) converters provide the link between the analog world of transducers and the digital world of signal processing, computing, digital data collection, data storage on magnetic material or optical disks and data processing systems. Practical converters must use standard digital CMOS technology without requiring special processing options or processing steps. Scaling of digital technology into the submicron range results in a reduction of the supply voltage into the 1 V range and below. Designs in this field require special circuit techniques to solve this problem. Examples and practical designs will be discussed in this book. CMOS Integrated Analog-to-Digital and Digital-to-Analog Converters describes in depth converter specifications like Effective Number of Bits (ENOB), Spurious Free Dynamic Range (SFDR), Integral Non-Linearity (INL), Differential Non-Linearity (DNL) and sampling clock jitter requirements. Relations between these specifications and practical issues like matching of components and offset parameters of differential pairs are derived. CMOS Integrated Analog-to-Digital and Digital-to-Analog Converters describes the requirements of input and signal reconstruction filtering in case a converter is applied into a signal processing system. CMOS Integrated Analog-to-Digital and Digital-to-Analog Converters describes design details of high-speed A/D and D/A converters, high-resolution A/D and D/A converters, sample-and-hold amplifiers, voltage and current references, noise-shaping converters and sigma-delta converters, technology parameters and matching performance, comparators and limitations of comparators and finally testing of converters. CMOS Integrated Analog-to-Digital and Digital-to-Analog Converters is the second edition of the most comprehensive book available on this subject. It contains an extensive bibliography and an index to all subjects. CMOS Integrated Analog-to-Digital and Digital-to-Analog Converters describes in an innovative manner the small signal stability of noise-shaping 1-bit and multi-bit coders and sigma-delta converters. CMOS Integrated Analog-to-Digital and Digital-to-Analog Converters is an ideal book for use in advanced courses and is an essential reference for researchers and practicing system and circuit designers in this field.
Book Info
Text describes the requirements of input and signal reconstruction filtering. Describes design details of high-speed A/D and D/A converters, high-resolution A/D and D/A converters, sample-and-hold amplifiers, and more. For researchers and practitioners.
1 The converter as a black box 1
1.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.2 Basic D/A and A/D converter function . . . . . . . . . . . . 2
1.3 Classification of signals . . . . . . . . . . . . . . . . . . . . . . 5
1.3.1 Different signal conditions . . . . . . . . . . . . . . . . 5
1.3.2 Analog signals . . . . . . . . . . . . . . . . . . . . . . 5
1.3.3 Discrete-time signals . . . . . . . . . . . . . . . . . . . 6
1.3.4 Amplitude-discrete signals . . . . . . . . . . . . . . . . 6
1.3.5 Digital signals . . . . . . . . . . . . . . . . . . . . . . . 6
1.4 Quantization errors . . . . . . . . . . . . . . . . . . . . . . . . 7
1.5 Oversampling of converters . . . . . . . . . . . . . . . . . . . 10
1.6 Quantization error spectra . . . . . . . . . . . . . . . . . . . . 12
1.7 Amplitude dependence of quantization components . . . . . . 16
1.8 Multiple signal distortion . . . . . . . . . . . . . . . . . . . . 17
1.9 Accurate dynamic range calculation . . . . . . . . . . . . . . 19
1.10 Sampling time uncertainty . . . . . . . . . . . . . . . . . . . . 21
1.10.1 Reduction of ENOB by sampling clock jitter . . . . . 23
1.11 Sampling clock time uncertainty . . . . . . . . . . . . . . . . 25
1.12 Conversion systems . . . . . . . . . . . . . . . . . . . . . . . . 27
1.12.1 Sampling with no-aliasing . . . . . . . . . . . . . . . . 28
1.12.2 Sampling with aliasing . . . . . . . . . . . . . . . . . . 29
1.12.3 Sampling of quantization errors . . . . . . . . . . . . . 29
1.13 Nyquist filtering in A/D converter systems . . . . . . . . . . . 31
1.14 Combined analog and digital filter . . . . . . . . . . . . . . . 32
1.15 Output filtering in D/A converter systems . . . . . . . . . . . 34
1.16 Dynamic range and alias filter order . . . . . . . . . . . . . . 41
1.17 Analog filter designs . . . . . . . . . . . . . . . . . . . . . . . 42
1.17.1 Fourth order Butterworth filter . . . . . . . . . . . . . 42
1.17.2 Fifth order Butterworth filter . . . . . . . . . . . . . . 43
1.17.3 Digital filter design . . . . . . . . . . . . . . . . . . . . 45
1.18 Minimum required stop band attenuation . . . . . . . . . . . 45
1.19 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Specifications of converters
2.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.2 Digital data coding . . . . . . . . . . . . . . . . . . . . . . . .
2.3 Digital coding schemes . . . . . . . . . . . . . . . . . . . . . .
2.4 Ideal and Non-ideal converters . . . . . . . . . . . . . . . . .
2.5 DC specifications . . . . . . . . . . . . . . . . . . . . . . . . .
2.5.1 Absolute accuracy . . . . . . . . . . . . . . . . . . . .
2.5.2 Relative accuracy . . . . . . . . . . . . . . . . . . . . .
2.5.3 Nonlinearity calculation . . . . . . . . . . . . . . . . .
2.5.4 Differential nonlinearity . . . . . . . . . . . . . . . . .
2.5.5 Offset . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.5.6 Temperature dependence . . . . . . . . . . . . . . . .
2.5.7 Supply voltage . . . . . . . . . . . . . . . . . . . . . .
2.6 Dynamic specifications . . . . . . . . . . . . . . . . . . . . . .
2.6.1 Signal-to-Noise Ratio . . . . . . . . . . . . . . . . . . .
2.6.2 Spurious Free Dynamic Range . . . . . . . . . . . . .
2.6.3 Effective Number Of Bits (ENOB's) . . . . . . . . . .
2.6.4 Dynamic range versus converter linearity . . . . . . .
2.6.5 Required accuracy of converter elements . . . . . . . .
2.6.6 Element matching versus INL of 8 to 14 bit converters
2.6.7 ENOB and SFDR versus INL converter model . . . .
2.6.8 Intermodulation modeling . . . . . . . . . . . . . . . .
2.6.9 Glitches . . . . . . . . . . . . . . . . . . . . . . . . . .
2.6.10 Noise . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.6.11 Minimum reference step size . . . . . . . . . . . . . . .
2.6.12 Bit Error Rate (BER) . . . . . . . . . . . . . . . . . .
2.6.13 Maximum sampling rate . . . . . . . . . . . . . . . . .
2.6.14 Digital signal feed-through . . . . . . . . . . . . . . .
2.6.15 Distortion . . . . . . . . . . . . . . . . . . . . . . . . .
2.6.16 Power supply rejection ratio . . . . . . . . . . . . . . . 96
2.6.17 Settling time . . . . . . . . . . . . . . . . . . . . . . . 96
2.6.18 Acquisition time . . . . . . . . . . . . . . . . . . . . . 96
2.6.19 Aperture time . . . . . . . . . . . . . . . . . . . . . . 97
2.6.20 Sample-to-hold step . . . . . . . . . . . . . . . . . . . 99
2.6.21 Droop rate . . . . . . . . . . . . . . . . . . . . . . . . 99
2.6.22 Signal feed-through during hold mode . . . . . . . . . 100
2.6.23 Noise in sample-and-hold amplifiers . . . . . . . . . . 100
2.6.24 Overview of sample-and-hold specifications . . . . . . 101
2.6.25 Analog system bandwidth . . . . . . . . . . . . . . . . 102
2.6.26 Differential gain and differential phase . . . . . . . . . 103
2.7 Figure of Merit . . . . . . . . . . . . . . . . . . . . . . . . . . 103
2.8 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
3 High-speed A/D converters 107
3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
3.2 Design problems in high-speed converters . . . . . . . . . . . 110
3.2.1 Timing errors . . . . . . . . . . . . . . . . . . . . . . . 110
3.2.2 Distortion . . . . . . . . . . . . . . . . . . . . . . . . . 111
3.3 Internal converter coding schemes . . . . . . . . . . . . . . . . 112
3.3.1 Thermometer code . . . . . . . . . . . . . . . . . . . . 112
3.3.2 Gray encoder . . . . . . . . . . . . . . . . . . . . . . . 113
3.3.3 Circular code . . . . . . . . . . . . . . . . . . . . . . . 114
3.4 Full-flash converters . . . . . . . . . . . . . . . . . . . . . . . 115
3.4.1 Comparator input amplifier . . . . . . . . . . . . . . . 116
3.5 Interpolation . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
3.5.1 DNL Improvement by interpolation . . . . . . . . . . 119
3.5.2 Multiple interpolation . . . . . . . . . . . . . . . . . . 120
3.5.3 Multiple interpolation error . . . . . . . . . . . . . . . 121
3.5.4 Active interpolation . . . . . . . . . . . . . . . . . . . 122
3.5.5 Capacitive interpolation . . . . . . . . . . . . . . . . . 123
3.6 Averaging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
3.6.1 Averaging non-linearity error . . . . . . . . . . . . . . 126
3.6.2 Averaging non-linearity compensation . . . . . . . . . 127
3.6.3 Moebius band averaging compensation . . . . . . . . . 128
3.6.4 Activeaveragingsystem . . . . . . . . . . . . . . . . . 128
3.7 6-bit converter implementation . . . . . . . . . . . . . . . . . 130
3.7.1 Differential input amplifier system . . . . . . . . . . . 131
3.7.2 Second and third amplifier stages . . . . . . . . . . . . 132
3.7.3 ENOB measurement of 6-bit converter . . . . . . . . . 132
3.7.4 Specification of 6-bit converter . . . . . . . . . . . . . 134
3.8 Discrete time flash converter . . . . . . . . . . . . . . . . . . 134
3.8.1 Second amplifier stage . . . . . . . . . . . . . . . . . . 137
3.9 Gray code full flash converters . . . . . . . . . . . . . . . . . 138
3.10 Circular code flash converters . . . . . . . . . . . . . . . . . . 142
3.11 Two-step flash converters . . . . . . . . . . . . . . . . . . . . 144
3.11.1 Two-step A/D converter implementation . . . . . . . . 145
3.11.2 Two-step capacitive MDAC AID converter . . . . . . 147
3.12 Sub ranging converter architecture . . . . . . . . . . . . . . . 148
3.12.1 8-bit Sub ranging converter implementation . . . . . . 150
3.12.2 Coarse comparator . . . . . . . . . . . . . . . . . . . . 151
3.12.3 Fine comparator . . . . . . . . . . . . . . . . . . . . . 152
3.12.4 Reference ladder construction . . . . . . . . . . . . . . 152
3.12.5 Interleaved comparator flash converter . . . . . . . . . 153
3.12.6 Interleaved comparator two-step AID converter . . . . 154
3.12.7 10-bit subrange converter . . . . . . . . . . . . . . . . 157
3.12.8 Coarse converter stage . . . . . . . . . . . . . . . . . . 158
3.12.9 Fine converter stage . . . . . . . . . . . . . . . . . . . 159
3.12.10 10-bit converter data . . . . . . . . . . . . . . . . . . . 160
3.13 Pipeline converter architecture . . . . . . . . . . . . . . . . . 160
3.13.1 Single bit per stage sub-converter architecture . . . . . 161
3.13.2 Multi-bit pipeline converter . . . . . . . . . . . . . . . 164
3.13.3 Sharing amplifiers in pipeline converters . . . . . . . . 166
3.14 Folding converter system . . . . . . . . . . . . . . . . . . . . . 169
3.14.1 Current-folding A/D converter system . . . . . . . . . 170
3.14.2 7-bit current folding implementation . . . . . . . . . . 171
3.14.3 Improved current folding system . . . . . . . . . . . . 172
3.14.4 Fine converter system . . . . . . . . . . . . . . . . . . 173
3.14.5 High-frequency rounding problem . . . . . . . . . . . . 174
3.14.6 Double folding system . . . . . . . . . . . . . . . . . . 174
3.14.7 8-bit folding and interpolation converter . . . . . . . . 176
3.14.8 Transimpedance amplifier . . . . . . . . . . . . . . . . 177
3.14.9 Transimpedance amplifier circuit diagram . . . . . . . 178
3.14.10 Resistive interpolation . . . . . . . . . . . . . . . . . . 179
3.14.11 Comparator circuit . . . . . . . . . . . . . . . . . . . . 179
3.14.12 Converter specifications . . . . . . . . . . . . . . . . . 181
3.14.13 Distributed S/H folding and interpolation converter . 181
3.14.14Distributed T/H folding and interpolation converter
architecture . . . . . . . . . . . . . . . . . . . . . . . . 1 83
3.14.15 Track-and-hold circuit implementation . . . . . . . . . 184
3.14.16 Cascaded folding block architecture . . . . . . . . . . 185
3.14.17 Triple folding block circuit diagram . . . . . . . . . . . 187
3.14.18 Coarse code generation . . . . . . . . . . . . . . . . . 188
3.14.19 Measurements . . . . . . . . . . . . . . . . . . . . . . 188
3.14.20 8-bit distributed T/H folding and interpolation converter
specifications . . . . . . . . . . . . . . . . . . . 188
3.14.21 10-bit folding and averaging converter . . . . . . . . . 190
3.14.22 Improved averaging . . . . . . . . . . . . . . . . . . . 190
3.14.23 Drain load current sources . . . . . . . . . . . . . . . . 192
3.14.24 Differential converter input system . . . . . . . . . . . 193
3.14.25 Comparator circuit diagram . . . . . . . . . . . . . . . 194
3.14.26 Measurements . . . . . . . . . . . . . . . . . . . . . . 195
3.14.27 10-bit converter specifications . . . . . . . . . . . . . . 195
3.15 Time interleaved high-speed converters . . . . . . . . . . . . . 195
3.16 Minimum supply voltage calculation . . . . . . . . . . . . . . 198
3.17 Reference ladder signal feedthrough . . . . . . . . . . . . . . . 199
3.18 Bubble correction . . . . . . . . . . . . . . . . . . . . . . . . . 200
3.19 Delay over interconnect lines . . . . . . . . . . . . . . . . . . 201
3.20 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203
4 High-speed D/A converters 205
4.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205
4.2 High-speed D/A converter architectures . . . . . . . . . . . . 205
4.2.1 Binary weighted converter coding . . . . . . . . . . . . 206
4.2.2 Fully segmented converter architecture . . . . . . . . . 206
4.2.3 Partially segmentation combined with binary weighting
converter architecture . . . . . . . . . . . . . . . . 206
4.3 Voltage weighting based architecture . . . . . . . . . . . . . . 208
4.3.1 Dual-ladder 10-bit D/A converter . . . . . . . . . . . . 208
4.3.2 Equal currents output ladder network . . . . . . . . . 212
4.3.3 Data interleaved D/A converter . . . . . . . . . . . . . 213
4.4 High-speed segmented converter architecture . . . . . . . . . 214
4.4.1 10-bit 500 Msamples/sec digital-to-analog converter . 216
4.4.2 Measurement results of 500 Msamples/s 10-bit converter219
4.4.3 A 10-bit 1-Gsample/s Nyquist digital-to-analog converter
. . . . . . . . . . . . . . . . . . . . . . . . . . . 221
4.4.4 Current matrix floor plan . . . . . . . . . . . . . . . . 222
4.4.5 Switch and latch circuit . . . . . . . . . . . . . . . . . 222
4.4.6 Measurement results of 1-Gsamplels 10-bit converter . 223
4.4.7 12-bit 500 Msamplels digital-to-analog converter . . . 224
4.4.8 Measurement results of the 12-bit 500 Msample/s digital-
to-analog converter . . . . . . . . . . . . . . . . . . . . 225
4.4.9 Influence of wire delay on high-frequency performance 225
4.4.10 Digital-to-analog converter switching network model . 227
4.4.11 SFDR and delay calculation model . . . . . . . . . . . 2 29
4.4.12 Output impedance of current cells . . . . . . . . . . . 231
4.4.13 Calculation of minimum current cell output impedance 233
4.5 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . 234
5 High-resolution A/D converters 237
5.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 37
5.2 Single slope A/D converter system . . . . . . . . . . . . . . . 238
5.3 Dual-slope A/D converter system . . . . . . . . . . . . . . . . 240
5.4 Dual-ramp single-slope A/D converter system . . . . . . . . . 241
5.4.1 Accuracy analysis of the dual ramp A/D converter . . 243
5.5 Successive approximation converter system . . . . . . . . . . 244
5.5.1 Successive approximation A/D converter examples . . 246
5.5.2 Digital-to-analog converter . . . . . . . . . . . . . . . 2 46
5.5.3 Current subtraction circuit . . . . . . . . . . . . . . . 247
5.5.4 Micropower successive approximation A/D converter . 248
5.5.5 Current subtracter/comparator circuit diagram . . . . 250
5.5.6 12-bit switched capacitor successive approximation con-
verter . . . . . . . . . . . . . . . . . . . . . . . . . . . 251
5.6 Algorithmic AID converter . . . . . . . . . . . . . . . . . . . 254
5.7 Cyclic Redundant Signed Digit AID converter . . . . . . . . 256
5.8 Self-calibrating capacitor A/D converter . . . . . . . . . . . . 260
5.9 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . 262
6 High-resolution D/A converters 263
6.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . 263
6.2 Pulse-width modulation D/A converters . . . . . . . . . . . . 264
6.3 Integrating D/A converters . . . . . . . . . . . . . . . . . . . 266
6.4 Current weighting using ladder networks . . . . . . . . . . . . 270
6.4.1 R-2Rladder network . . . . . . . . . . . . . . . . . . . 270
6.4.2 MOS only binary weighted current network . . . . . . 271
6.4.3 MOS R-2R implementation . . . . . . . . . . . . . . . 273
6.4.4 4-bit R-2R MOS converter example . . . . . . . . . . 274
6.4.5 Two-step current division network . . . . . . . . . . . 275
6.4.6 MOS ladder network converter system . . . . . . . . . 276
6.4.7 Weighted capacitor converter system . . . . . . . . . . 277
6.4.8 Weighted capacitor network with output amplifier . . 278
6.4.9 Weighted capacitor network with resistive interpolation279
6.5 Monotonic by design network systems . . . . . . . . . . . . . 280
6.5.1 Voltage division operation . . . . . . . . . . . . . . . . 281
6.5.2 Current weighting operation . . . . . . . . . . . . . . . 283
6.5.3 MOS only monotonic by design system . . . . . . . . . 284
6.5.4 Active division MOS only monotonic by design system 285
6.5.5 Current-to-voltage converter . . . . . . . . . . . . . . 286
6.6 Self calibrating D/A converter system . . . . . . . . . . . . . 287
6.7 Dynamic Element Matching . . . . . . . . . . . . . . . . . . . 289
6.7.1 Basic dynamic divider scheme . . . . . . . . . . . . . . 289
6.7.2 Practical dynamic divider circuit . . . . . . . . . . . . 292
6.7.3 Two-bit dynamic current divider scheme . . . . . . . . 293
6.7.4 Dynamic current mirror circuit . . . . . . . . . . . . . 296
6.7.5 Binary-weighted accurate current network . . . . . . . 297
6.7.6 Binary-weighted current network with divided interchanging
clock . . . . . . . . . . . . . . . . . . . . . . 298
6.7.7 Binary-weighted current network using equal interchanging
clock frequencies . . . . . . . . . . . . . . . . 299
6.7.8 16-bit binary network example . . . . . . . . . . . . . 299
6.7.9 Filtering and switching . . . . . . . . . . . . . . . . . 300
6.7.10 Randomizer to avoid ripple filtering . . . . . . . . . . 301
6.8 Current calibration principle . . . . . . . . . . . . . . . . . . 302
6.8.1 Improved current calibration principle . . . . . . . . . 305
6.8.2 Continuous current calibration system . . . . . . . . . 306
6.8.3 Practical current calibration implementation . . . . . 306
6.8.4 16-bit D/A converter system . . . . . . . . . . . . . . 307
6.8.5 Integral nonlinearity measurement . . . . . . . . . . . 309
6.8.6 Dynamic performance measurement . . . . . . . . . . 309
6.8.7 D/A converter specifications . . . . . . . . . . . . . . 310
6.8.8 Some remarks about the ladder converter systems . . 310
6.9 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . 311
7 Sample-and-hold amplifiers 313
7.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . 313
7.2 Basic sample-and-hold configuration . . . . . . . . . . . . . . 314
7.2.1 Signal bandwidth . . . . . . . . . . . . . . . . . . . . . 314
7.2.2 Acquisition time . . . . . . . . . . . . . . . . . . . . . 315
7.2.3 Aperture time accuracy . . . . . . . . . . . . . . . . . 316
7.2.4 Sampli7.2.5 Differential sample-and-hold circuit . . . . . . . . . . . 318
7.2.6 Sample clock bootstrapping . . . . . . . . . . . . . . . 320
7.2.7 Differential sampling clock bootstrap circuit . . . . . . 321
7.2.8 Low signal feedthrough switch . . . . . . . . . . . . . 322
7.2.9 Time interleaved sample-and-hold . . . . . . . . . . . 3 23
7.2.10 Signal dependent clock bootstrapping . . . . . . . . . 324 1
7.2.11 Simple signal clock bootstrap system . . . . . . . . . . 324
7.2.12 Modified signal clock bootstrap system . . . . . . . . . 326
7.2.13 Gate and bulk bootstrapping system . . . . . . . . . . 326
7.2.14 Double sided bootstrapping . . . . . . . . . . . . . . . 327
7.2.15 Sample and hold mode errors . . . . . . . . . . . . . . 328
7.2.16 MOS switch charge injection . . . . . . . . . . . . . . 3 29
7.2.17 Noise in sample-and-hold circuits . . . . . . . . . . . . 333 ~
7.3 Generalized non-inverting configurations . . . . . . . . . . . . 335 I
7.3.1 Double-buffered sample-and-hold circuit . . . . . . . . 335
7.3.2 Feedback improved sample-and-hold circuit . . . . . . 336 I
7.3.3 Integrating sample-and-hold circuit . . . . . . . . . . . 336
7.3.4 Practical integrating S/H circuit . . . . . . . . . . . . 337
7.3.5 Switched capacitor sample-and-hold circuit . . . . . . 338
7.3.6 Switched capacitor sample-and-hold circuit with gain . 339
7.3.7 CMOS non-inverting mode S/H example . . . . . . . . 340
7.3.8 MOS differential sample-and-hold . . . . . . . . . . . . 3 42 I
7.3.9 Sample-and-hold amplifier with full hold time . . . . . 344
7.4 Inverting sample-and-hold circuit . . . . . . . . . . . . . . . . 345
7.5 Operational range of simple sample-and-hold amplifiers . . . 346
7.6 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . 347
8 Noise-shaping D/A conversion 349
8.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . 349
8.2 Digital oversampling filtering . . . . . . . . . . . . . . . . . . 350
8.2.1 Combined digital-analog D/A output filter . . . . . . 351
8.2.2 Digital filter configuration . . . . . . . . . . . . . . . . 352
8.2.3 Quantization errors 353 ~ . . . . . . . . . . . . . . . . . . . .
8.3 Noise-shaping . . . . . . . . . . . . . . . . . . . . . . . . . . . 353
8.3.1 Single bit digital-to-analog converter . . . . . . . . . . 355
8.3.2 Multi-bit digital-to-analog converter . . . . . . . . . . 356
8.3.3 First-order noise-shaper . . . . . . . . . . . . . . . . . 357
8.3.4 Second-order noise-shaper . . . . . . . . . . . . . . . . 360 I
8.3.5 Third-order noise-shaper . . . . . . . . . . . . . . . . . 361
8.3.6 Fourth-, fifth-, and sixth-order noise-shaper . . . . . . 364
8.3.7 Largely oversampled noise-shaper . . . . . . . . . . . . 369
8.4 Multi-bit largely oversampled noise-shaper . . . . . . . . . . . 370
8.5 Stability analysis of noise-shapers . . . . . . . . . . . . . . . . 371
8.5.1 Noise-shaper stability model . . . . . . . . . . . . . . . 372
8.5.2 Root Locus stability analysis method . . . . . . . . . . 373
8.5.3 First-order system . . . . . . . . . . . . . . . . . . . . 374
8.5.4 Second-order system . . . . . . . . . . . . . . . . . . . 374
8.5.5 Simulation of second order system . . . . . . . . . . . 375
8.5.6 Third-order system . . . . . . . . . . . . . . . . . . . . 375
8.5.7 Quantizer describing function model . . . . . . . . . . 379
8.5.8 Maximum global gain calculation . . . . . . . . . . . . 383
8.5.9 Extended quantizer model . . . . . . . . . . . . . . . . 384
8.5.10 Root locus of second order system using extended quantizer
model . . . . . . . . . . . . . . . . . . . . . . . . 387
8.5.11 Third order 1-bit system using the extended quantizer
model . . . . . . . . . . . . . . . . . . . . . . . . . . . 388
8.5.12 Multi-bit system analysis . . . . . . . . . . . . . . . . 389
8.6 Practical noise-shaping D/A converters . . . . . . . . . . . . . 391
8.6.1 16-bit D/A converter system . . . . . . . . . . . . . . 391
8.6.2 18-bit D/A converter system . . . . . . . . . . . . . . 395
8.6.3 Continuous time FIR reconstruction filter D/A converter398
8.6.4 Combined digital-analog FIR filter architecture . . . . 399
8.6.5 FIR filter response . . . . . . . . . . . . . . . . . . . . 400
8.6.6 Total filter response . . . . . . . . . . . . . . . . . . . 402
8.6.7 Converter specification . . . . . . . . . . . . . . . . . . 402
8.7 Multi-bit noise-shaping D/A converter . . . . . . . . . . . . . 403
8.7.1 Multi-bit system configuration . . . . . . . . . . . . . 403
8.7.2 Detail of sign-magnitude converter . . . . . . . . . . . 405
8.7.3 Sign-magnitude self-calibration system . . . . . . . . . 405
8.7.4 Total system implementation . . . . . . . . . . . . . . 406
8.7.5 Multi-bit digital-to-analog converter using randomized
Dynamic Element Matching . . . . . . . . . . . . . . . 407
8.7.6 Non-filtered DEM D/A architecture . . . . . . . . . . 408
8.7.7 Resistive element DEM D/A converter . . . . . . . . . 409
8.7.8 Randomizer system . . . . . . . . . . . . . . . . . . . 410
8.7.9 Super audio 24-bit D/A converter . . . . . . . . . . . 410
8.7.10 15-level capacitive DEM D/A converter . . . . . . . . 411
8.7.11 Differential dual 31-level DEM D/A converter . . . . . 412
8.7.12 Third order noise-shaper architecture . . . . . . . . . 413
8.7.13 Comparison between conventional DWA and partial
DWA system architecture . . . . . . . . . . . . . . . . 4 13
8.7.14 24-bit D/A converter performance . . . . . . . . . . . 413
8.8 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . 415
9 Sigma-delta A/D conversion 417
9.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . 417
9.2 General form of Sigma-delta AID converters . . . . . . . . . . 418
9.2.1 Dynamic range . . . . . . . . . . . . . . . . . . . . . . 422
9.3 General filter architectures . . . . . . . . . . . . . . . . . . . . 423
9.3.1 1-bit Sigma-delta signal examples . . . . . . . . . . . . 425
9.3.2 Multi-bit Sigma-delta signal examples . . . . . . . . . 426
9.3.3 Return-to-zero D/A pulse . . . . . . . . . . . . . . . . 427
9.3.4 Continuous time filter first order converter . . . . . . 428
9.3.5 Fully continuous time first order converter . . . . . . . 430 I
9.4 Discussion of basic converter architectures . . . . . . . . . . . 432
9.4.1 First-order AID converter . . . . . . . . . . . . . . . . 432
9.4.2 Second-order AID converter . . . . . . . . . . . . . . . 433
9.4.3 Third-order A/D converter . . . . . . . . . . . . . . . 435
9.5 Multi-stage sigma-delta converter (MASH) . . . . . . . . . . 437
9.6 Quantizer overload avoidance . . . . . . . . . . . . . . . . . . 438
9.6.1 Interstage gain scaling in cascaded converters . . . . . 439
9.6.2 Local feedback system across individual integrators . . 440
9.6.3 Gain scaling and local feedback in cascaded converters 440
9.7 Converter input circuitry . . . . . . . . . . . . . . . . . . . . 441
9.7.1 Cross-coupled input sampling . . . . . . . . . . . . . . 443
9.7.2 Clock timing scheme . . . . . . . . . . . . . . . . . . . 444 1
9.7.3 Shared capacitor input circuit . . . . . . . . . . . . . . 444
9.8 Practical 16-bit cascaded converter . . . . . . . . . . . . . . . 445
9.8.1 Converter specifications . . . . . . . . . . . . . . . . . 445
9.9 Feed-forward AID converter system . . . . . . . . . . . . . . 445
9.9.1 Continuous time input circuit . . . . . . . . . . . . . . 448
9.9.2 Intermediate stage circuit diagram . . . . . . . . . . . 450
9.9.3 Simulated noise transfer function . . . . . . . . . . . . 451
9.10 Nth-order sigma-delta architecture . . . . . . . . . . . . . . . 451
9.11 Bandpass sigma-delta converters . . . . . . . . . . . . . . . . 454
9.12 Low-pass to band-pass transformation . . . . . . . . . . . . . 454
9.12.1 Switched capacitor implementation . . . . . . . . . . . 454
9.12.2 Switched capacitor N-path architecture . . . . . . . . 455
9.12.3 Two-path band-pass converter architecture . . . . . . 455
9.12.4 Two-path circuit implementation . . . . . . . . . . . . 457
9.13 Continuous time band-pass converter . . . . . . . . . . . . . . 458
9.13.1 Band-pass filter architecture . . . . . . . . . . . . . . . 458
9.13.2 Differential amplifier implementation . . . . . . . . . . 460
9.13.3 Measurements sixth order band-pass converter . . . . 461
9.14 Limited gain in loop filter . . . . . . . . . . . . . . . . . . . . 463
9.15 Idle pattern . . . . . . . . . . . . . . . . . . . . . . . . . . . . 463
9.15.1 Threshold effect of a first-order converter . . . . . . . 466
9.15.2 Threshold effect of a second-order converter . . . . . . 468
9.15.3 Dither signals . . . . . . . . . . . . . . . . . . . . . . . 468
9.15.4 Threshold signal distortion . . . . . . . . . . . . . . . 469
9.16 Sigma-delta digital voltmeter . . . . . . . . . . . . . . . . . . 469
9.16.1 Auto-zero circuit . . . . . . . . . . . . . . . . . . . . . 472
9.16.2 Analog subsystem implementation . . . . . . . . . . . 473
9.16.3 Complete digital voltmeter system . . . . . . . . . . . 474
9.17 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . 475
10 Voltage and current references 477
10.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . 477
10.2 Gate-source voltage used as a reference . . . . . . . . . . . . . 477
10.2.1 Improved gate-source voltage stabilizer . . . . . . . . . 478
10.3 Basic band-gap reference voltage source . . . . . . . . . . . . 479
10.3.1 Practical band-gap voltage source . . . . . . . . . . . 483
10.4 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . 484
11 Limitations of comparators 485
11.1 Signal delay in limiting amplifiers . . . . . . . . . . . . . . . . 485
11.1.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . 485
11.2 Definition of the delay problem . . . . . . . . . . . . . . . . . 486
11.3 Delay calculation model . . . . . . . . . . . . . . . . . . . . . 487
11.4 Variable delay calculation . . . . . . . . . . . . . . . . . . . . 489
11.5 Distortion calculation . . . . . . . . . . . . . . . . . . . . . . 495
11.6 Failure analysis of comparators . . . . . . . . . . . . . . . . . 499
11.6.1 First-order model of a flip-flop . . . . . . . . . . . . . 499
11.6.2 BER simulation . . . . . . . . . . . . . . . . . . . . . . 503
11.7 Current mode comparator circuit . . . . . . . . . . . . . . . . 504
11.8 Differential auto-zero comparator . . . . . . . . . . . . . . . . 506
11.9 Complementary comparator with latch . . . . . . . . . . . . . 508
11.1OLow kick back comparator implementation . . . . . . . . . . . 509
11.11Input frequency decision moment variation . . . . . . . . . . 510
xii CONTENTS
12 Technology and device matching 513
12.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . 513
12.2 Technology road map . . . . . . . . . . . . . . . . . . . . . . . 513
12.3 MOS matching models . . . . . . . . . . . . . . . . . . . . . . 5 14
12.4 Capacitor matching . . . . . . . . . . . . . . . . . . . . . . . . 520
12.5 Resistor matching . . . . . . . . . . . . . . . . . . . . . . . . 521
12.6 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . 522
13 Testing of D/A and A/D converters 523
13.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . 523
13.2 DC testing of D/A converters . . . . . . . . . . . . . . . . . . 523
13.2.1 Temperature relations . . . . . . . . . . . . . . . . . . 525
13.2.2 Supply voltage dependence . . . . . . . . . . . . . . . 525
13.2.3 Bit weight noise . . . . . . . . . . . . . . . . . . . . . 525
13.3 Dynamic testing of D/A converters . . . . . . . . . . . . . . . 526
13.3.1 Dynamic integral nonlinearity test . . . . . . . . . . . 527
13.3.2 Spurious free dynamic range . . . . . . . . . . . . . . 527
13.3.3 Differential nonlinearity . . . . . . . . . . . . . . . . . 528
13.3.4 Glitches . . . . . . . . . . . . . . . . . . . . . . . . . . 528
13.3.5 Distortion measurement . . . . . . . . . . . . . . . . . 529
13.3.6 Settling time measurement . . . . . . . . . . . . . . . 529
13.4 DC testing of AID converters . . . . . . . . . . . . . . . . . . 531
13.5 Dynamic testing of A/D converters . . . . . . . . . . . . . . . 532
13.5.1 Conversion speed . . . . . . . . . . . . . . . . . . . . . 534
13.6 Bit Error Rate . . . . . . . . . . . . . . . . . . . . . . . . . . 535
13.7 Testing very high-speed A/D converters . . . . . . . . . . . . 536
13.8 Beat frequency test configuration . . . . . . . . . . . . . . . . 539
13.9 Code density DNL and INL measurement . . . . . . . . . . . 540
13.10Testing of sample-and-hold amplifiers . . . . . . . . . . . . . . 544
13.10.1 Testing DC characteristics . . . . . . . . . . . . . . . . 545
13.10.2 Dynamic measurements . . . . . . . . . . . . . . . . . 545
13.11 Cascading sample-and-hold amplifiers . . . . . . . . . . . . . 548
13.12Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . 549 |
