Digital VLSI Design with Verilog
A Textbook from Silicon Valley Technical Institute

Williams, John

2008, Approx. 460 p. With CD-ROM., Hardcover
ISBN: 978-1-4020-8445-4

Not yet published. Available: August 3, 2008

 
$149.00

 
About this book
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Table of contents

About this book

Covers the entire verilog language
Includes a multiple-lab project in development of a large serialization device
Uses simulation examples to teach the writing of code for correct netlist synthesis
Shows the use of assertions for the verilog and design-for-test methodology for the hardware
Includes a CD-ROM with verilog netlist libraries and answers for all lab exercises
This unique textbook is structured as a step-by-step course of study along the lines of a VLSI IC design project.
In a nominal schedule of 12 weeks, two days and about 10 hours per week, the entire verilog language is presented, from the basics to everything necessary for synthesis of an entire 70,000 transistor, full-duplex serializer - deserializer, including synthesizable PLLs.
Digital VLSI Design With Verilog is all an engineer needs for in-depth understanding of the verilog language: Syntax, synthesis semantics, simulation, and test. Complete solutions for the 27 labs are provided on the accompanying CD-ROM. For a reader with access to appropriate electronic design tools, all solutions can be developed, simulated, and synthesized as described in the book.
A partial list of design topics includes design partitioning, hierarchy decomposition, safe coding styles, back-annotation, wrapper modules, concurrency, race conditions, assertion-based verification, clock synchronization, and design for test.
Coverage of specific devices includes basic discussion and exercises on flip-flops, latches, combinational logic, muxes, counters, shift-registers, decoders, state machines, memories (including parity and ECC), FIFOs, and PLLs. Verilog specify blocks, with their path delays and timing checks, also are covered.
Written for:
Working engineers or engineering students interested in the design of digital IC's. Typical backgrounds of working engineers would be: Test engineering; analog design or test; digital design in VHDL

Keywords:

HDL
simulation
synthesis
verilog