As technology scales into nano-meter region, design and test of StaticRandom Access Memories (SRAMs) becomes a highly complex task. Processdisturbances and various defect mechanisms contribute to the increasingnumber of unstable SRAM cells with parametric sensitivity. Growingsizes of SRAM arrays increase the likelihood of cells with marginalstability and pose strict constraints on transistor parametersdistributions. Standard functional tests often fail to detect unstable SRAM cells.Undetected unstable cells deteriorate quality and reliability of theproduct as such cells may fail to retain the data and cause a systemfailure. Special design and test measures have to be taken to identifycells with marginal stability. However, it is not sufficient toidentify the unstable cells. To ensure reliable system operation,unstable cells have to be repaired. CMOS SRAM Circuit Design and Parametric Test in Nano-ScaledTechnologies covers a broad range of topics related to SRAM design andtest. From SRAM operation basics through cell electrical and physicaldesign to process-aware and economical approach to SRAM testing. Theemphasis of the book is on challenges and solutions of stabilitytesting as well as on development of understanding of the link betweenthe process technology and SRAM circuit design in modern nano-scaledtechnologies.
